Overview
I am a CPU Physical Design Engineer at Apple working on hardware technologies and next-generation CPU cores. I graduated with my M.S. in Computer Engineering from the Electrical and Computer Engineering department at UC San Diego in December 2025.
I operate at the intersection of low-level hardware design and advanced software systems, with a passion for automating complex workflows and optimizing system performance. My experience spans CPU physical design, VLSI CAD automation, and high-performance computing (HPC) scaling.
Experience
Apple Inc.
CPU Physical Design Engineer
February 2026 — PresentFocused on physical implementation, place-and-route, and timing closure flows to optimize next-generation Apple Silicon CPU cores.
CPU Physical Design Intern
June 2025 — September 2025Contributed to the synthesis, place-and-route, and timing closure of high-performance CPU sub-systems, translating logic designs into physical layouts under strict power-delay targets.
SoC CAD Intern
June 2024 — September 2024Built automated logic verification scripts for a frontend VLSI CAD synthesis flow, specializing in Logic Equivalency Checking (LEC) and Engineering Change Order (ECO) automation.
University of California San Diego
CSE 140L Teaching Assistant
September 2025 — December 2025Directed digital design lab sessions, managed grading workflows, and prepared laboratory environments to help students master Verilog HDL and physical logic implementations.
CSE 240A Teaching Assistant
January 2025 — March 2025Developed homework assignments and guided graduate students through advanced computer architecture topics, including pipelining, out-of-order execution, and memory coherency.
CSE 140L Teaching Assistant
September 2024 — December 2024Directed digital design lab sessions and engineered a custom Python autograder to verify student-designed Verilog circuits from the ground up.
Lawrence Berkeley National Laboratory
Student Assistant
June 2023 — September 2023Modeled energy consumption profiles on the Perlmutter supercomputer to guide future green procurements, presenting power-performance trade-offs at the SC23 Sustainable Computing Workshop.
San Diego Supercomputer Center
HPC Software Engineer
November 2022 — June 2024A research group managed by Professor Yifeng Cui dedicated to developing and optimizing a world-class earthquake simulation application and preparing software for future exascale supercomputing facilities.
Ported and optimized world-class earthquake simulation codes (AWP and AWP-Topography) from CUDA to AMD HIP, preparing them to scale on exascale supercomputing facilities.
Nike Inc.
Software Engineer
June 2022 — September 2022Consolidated Nike’s product data streams from 12 internal APIs into unified, high-throughput AWS Lambda microservices, refining automated testing and telemetry logs for global scale.
Professional Career
Hot Chips Conference
Volunteer
August 24, 2025 — August 26, 2025Supported network infrastructure logs and logistics for the symposium at Stanford, engaging with microarchitecture designers and computing pioneers.
Volunteer
August 25, 2024 — August 27, 2024Supported network infrastructure logs and logistics for the symposium at Stanford, engaging with microarchitecture designers and computing pioneers.
Volunteer
August 26, 2023 — August 29, 2023Supported network infrastructure logs and logistics for the symposium at Stanford, engaging with microarchitecture designers and computing pioneers.
2MuchCache
Competition Team Member
April 2022 — December 20222MuchCache is UCSD's official team for the Student Cluster Competition 2022. The SCC22 tournament involved hosting, booting, and running multi-node HPC applications and benchmarks on physical high-density systems under a strict 3000W envelope.
Built a cluster telemetry dashboard and tuned clock frequencies for AMD EPYC and Instinct processors under a strict 3000W envelope, winning 1st Place in HPL and co-authoring a paper in IEEE TPDS.
Leadership & Initiatives
Academic Publications
Reproducibility of the DaCe Framework on NPBench Benchmarks
Comparing Power Signatures of HPC Workloads: Machine Learning vs Simulation
Education
Masters of Science in Computer Engineering
Focused on next-generation processor architectures, deep learning hardware accelerators, advanced VLSI layout pipelines, and high-performance cluster networking.
Bachelors of Science in Computer Engineering
Completed fundamental courses in low-level processor architecture, HDL logic verification, compiler construction, database models, and physical VLSI CAD.
Hobbies
A few of the personal interests and projects I explore outside of work:
A creative outlet to explore environmental composition, editing, and diverse photographic styles. View the gallery of 100+ exposures at photos.govind.cc.
Designing custom waveforms, patch routing, and modulating analog synthesis engines.
Building experimental applications, optimizing and automating tasks, and testing high-throughput systems.
Playing pickup games, staying active, and enjoying competition on the court.
Exploring speculative hard science fiction and non-fiction focusing on cosmic sociology, physics, and technological paradigms.
Exploring ways to optimize my daily life and workflows through LLMs and agentic systems.